SystemVerilog random data generate only for valid signal

I am new to SV and would like to get some opinions about randomization. I have two signals.

rand bit [20:0] data; rand bit data_valid;

I want to generate random data only when data_valid signal goes high. When valid signal is low, data should contain the previous signal. I have tried the following on

constraint valid_data {data -> data_valid ==1'b1; }

It generates random data when valid signal is high but then data becomes 0 when valid signal goes low. Is there any other way to do that? What I want is data signal should not change when valid becomes low.It should keep the current value of valid signal goes low.

Another issue is the randomization of data_valid signal. This is a 1 bit signal and I want to make this signal high randomly for 1 clock cycle only. At the moment it can remain high for any clock cycles which I don't want.