LFSR random number generator repeats too soon?

I'm developing a random number generator in VHDL using an LFSR. I'm using the example code given here: https://stackoverflow.com/a/43081797/9131627 This code works perfectly if I simulate it, but when I modify it to fit my needs, it stops working properly, and I'm not sure whats causing it.

My code is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prng is
  port (i_reset: in std_logic := '0';
        i_clk: in std_logic);
end prng; 

architecture behavioral of prng is
    signal bits: std_logic_vector(6 downto 0) := "0101000";
    signal random: std_logic_vector(6 downto 0);
begin
    process (i_clk)
        variable tmp: std_logic := '0';
    begin 
        if(rising_edge(i_clk)) then
            if(i_reset = '0') then
                tmp := bits(6) xor bits(5);
                bits <= tmp & bits(6 downto 1);
            end if;
        end if;
    end process;

    random <= bits;                
end architecture;

The main modification I've made is to change it to a 7-bit LFSR, using the taps 7 and 6, as recommended by Xilinx in the document here: https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

But my PRNG just randomises a few values and then starts to repeat the same sequence of 3 values. I have no idea why this is happening so can anyone check my code and offer some advice to help fix it?

The image below shows the number sequence. You can see the first few values are random, but then it repeats the sequence 109-54-91 indefinitely.