How to turn all rand_mode on effectively after partially turn them off in systermverilog

I have classes as below

class h1_c;
  rand bit[1:0] h1_a;
  rand bit[1:0] h1_b;
  h2_c h2;
  function new()
    h2 = mew();
  endfunction
endclass

class h2_c;
  rand bit[1:0] h2_a;
  rand bit[1:0] h2_b;
  h3_c h3;
  function new()
    h3 = mew();
  endfunction
endclass

class h3_c;
  rand bit[1:0] h3_a;
  rand bit[1:0] h3_b;
endclass

module p1;   
  h1_c h1;

  initial begin
    h1 = new();
    h1.h2.h2_a.rand_mode(0);
    h1.h2.h3.h3_a.rand_mode(0);
    h1.randomize();
    //How to turn all rand_mode on effectively after I turn them off seperately.
    //which like h1.*.rand_mode(1);
  end
endmodule

I turn some variables' rand mode off and want to turn them all on effectively after randomize(). Is there any efficient way to do that?