How to make a simualtion in verilog have different results everytime if it has random values?

I wanted to generate a different output of the same code every time i run it as it has random values assigned to some variables is there a way to do that for example seeding using time as in c ? Sample of a code that has the randomization in it

class ABC;

    rand bit [4 : 0] arr []; // dynamic array
    constraint arr_size{

        arr.size() >= 2;
        arr.size() <= 6;

    }


endclass 



module constraint_array_randomization();

ABC test_class;

initial begin 


    test_class = new();
    test_class.randomize();
    $display("The array has the value = %p ", test_class.arr);



end



endmodule