How to generate random time delay in VHDL

I want to implement a PUF using ring oscilator in VHDL, I need to generate 15 Ring Oscilator with different gate delays. Haw can I do that? My code is as follows:

generate_ros:
for i in 0 to 31 generate
ro_1: ring_oscilator 
    generic map (delay => 200 ps , chain_len => 15) -- 200ps shall be random
    port map (
      rst_i => s_rst,
      clk_o => s_inp(i)
    );
 end generate;