How to properly constraint signed multidimensional array for randomization in Systemverilog

I have created a signed multidimensional array declared as follows:

typedef logic signed [3:0][31:0] hires_frame_t;
typedef hires_frame_t [3:0] hires_capture_t;
hires_capture_t rndpacket;

I want to randomize this array such, that each element has value between -32768 to 32767, in 32-bit two's complement.

I've tried following:

assert(std::randomize(rndpacket) with
     {foreach (rndpacket[channel])
       foreach (rndpacket[channel][subsample])
          {rndpacket[channel][subsample] < signed'(32768);
           rndpacket[channel][subsample] >= signed'(-32768);}});

This compiles well, but (mentor graphics) modelsim fails in simulation claiming

randomize() failed due to conflicts between the following constraints:
#   clscummulativedata.sv(56): (rndpacket[3][3] < 32768);
#   cummulativedata.sv(57): (rndpacket[3][3] >= 32'hffff8000);

This is clearly something linked to usage of signed vectors. I had a feeling that everything should be fine as array is declared as signed as well as thresholds in the randomize, but apparently not. If I replace the range by 0-65535 everything works as expected.

What is the correct way to randomize such signed array?