Random Number Generator VHDL - FlipFlop and XOR Gates

I saw a lot of guides teaching how to generate a random number in VHDL, but i didn't understand anyone of them. Should i use FlipFlop data for this? I got an truth table that describes my Generator, but i didn't understand as well. My teacher told me that i have to use XOR gates, and a D FlipFlop with a clock. Can someone PLEASE help me with this? Generator Design