How to generate a duplicate random number sequence between SystemVerilog simulators?

I cowork a SystemVerilog project with someone. However, I am used to use Synopsys VCS SystemVerilog simulator and he is used to use Cadence INCISIVE irun.

One testbench module uses random numbers for generating test input pattern to top design module. Thus, I designed a class for generating random numbers:

class RandData;
    rand logic [3:0] randIn;
    function new(int seed);
        this.srandom(seed);
    endfunction
endclass

I can instantiate class RandData with a seed and get a fixed sequence of random numbers in simulations. However, the fixed random number sequence obtained by VCS is different from the fixed sequence by irun even if the same seed is used in two simulators.

Unfortunately, the golden output pattern of the top design module depends on the test input pattern. Thus, if a golden output pattern is generated with an input pattern generated by VCS, the golden output pattern will be mismatched to the top design output simulated by irun.

Thus, how can I make VCS and irun simulators generate a duplicate sequence of random numbers?