2 Bit Random number generator in HDL Verilog

I was attempting to write a R.N.G. in Verilog, im new.

Though I'm not sure if what I'm doing is correct.

module random(
input clk,
input rst_n,

output reg [1:0] data
);

reg [1:0] data_next;

always @* begin
data_next[1] = data[1]^data[0];
data_next[0] = data[0]^data_next[1];
end

always @(posedge clk or negedge rst_n)
if(!rst_n)
data <= 1'h1f;
else
data <= data_next;

endmodule

Any suggestions and guidance is appreciated.