system verilog - implementation of randomize()

I have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn't support this function.

I implemented a basic function in a class with the following member:

   bit [15:0]  data_xi;
   bit [15:0]  data_xq;

the basic random function:

   //function my_randomize
    function int my_randomize(int seed);
       int temp1, temp2;
      // temp = $urandom_range(1,11);
       temp1 = (($urandom(seed)) + 1);
       data_xi = temp1 - 1;
       temp2 = (($urandom(seed)) + 1);
       data_xq = temp2 - 1;
       if(temp1 != 0 || temp2 != 0 )
     return 1;
       else
     return 0;
    endfunction: my_randomize

Now I have to change it to global function which suppose to behave like randomize() with constraints.

How can I implement this?