Declaring class handle as rand type in System Verilog

Please See this for better clarification of of my codeWhat happens when we declare class handle as rand type? will it affect the randomization? I am trying to do sorting using constraint guards.

class Sorting;
    rand int unsigned n;
    rand Sorting next;
    constraint C0 { n inside {[2:20]};}

    constraint sort {if( next != null ) n < next.n;}

endclass

module random;
  Sorting s;
  initial
    begin
      s=new;
      repeat(10)
        begin
          assert(s.randomize());
          $write("%0d\t",s.n);
        end
    end
endmodule

I am getting the warning in VCS like these -> Warning-[CNST-PPRW] Constraint randomize NULL object warning

The same code is in the LRM under the constraint guard section. I am curious to know whether we can sort the random data using the constraint guard technique? I have done sorting the random data using foreach loop inside the constraint. I am just trying this way. Help me with it. Thanks!