Random value generator in VHDL

I am trying to generate some random values (only 1 and 0) for a VHDL testbench. I've tried the following code:

impure function rand_int(min_val, max_val : integer) return integer is
  variable r : real;
  variable seed1, seed2 : integer := 999;
begin
  uniform(seed1, seed2, r);
  return integer(round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;

but it only seems to be giving 1, and never 0. I can't understand where I'm doing wrong, any help would be greatly appreciated.