Single bit random number generator in Verilog

I am trying to generate single bit random number on every clock cycle in Verilog for testing purposes. I am doing this in testbench module. Here is the code;

module tb;

// Inputs
reg clk;
reg in;

// Outputs
wire x;

// Instantiate the Unit Under Test (UUT)
single_bit uut (
    .clk(clk), 
    .in(in), 
    .x(x)
);

integer seed=1;
initial
 begin
  clk=0;
  forever
    #5 clk=!clk;
        in= $random(seed);
end

endmodule

But after simulation, I am getting constant value of 1 in seed and in has x. Any help is appreciated.